With technical development in a computer system or a field of electronics and communications, a semiconductor memory device used for storing information comes to have a low cost, a reduced size and a large capacity, and demands for energy efficiency have also increased. Accordingly, technical development of semiconductor memory devices tends towards restriction of unnecessary current consumption.
In general, a cell array for storing data of a dynamic random access memory (DRAM) device has a structure in that a number of cells, each of which is formed of one n-type metal oxide silicon (NMOS) transistor and one capacitor, are respectively connected to word lines and bit lines, which are connected to each other in the form of a matrix.
Operation of a conventional DRAM device will be briefly described hereinafter.
First, when a /RAS signal or a main signal for operating a DRAM device goes into an active state (low level), address signals are inputted to a row address buffer and row decoding operation for decoding the inputted row address signals and selecting one of the word line in the cell array is then performed.
At this time, when data in the cells connected to the selected word line is loaded on a bit line pair formed of a bit line BL and a complementary bit line /BL, a sense amplifier enable signal indicating a time-point of operation of a sense amplifier is enabled to drive a sense amplifier driving circuit in a cell block selected by the row address. Further, sense amplifier bias voltages are shifted to a core voltage VCORE and a ground voltage VSS, respectively, by the sense amplifier driving circuit to drive a sense amplifier latch. When the sense amplifier latch begins to operate, a minute potential difference which is being maintained in the bit line pair BL, /BL is shifted to a large potential difference and a column decoder selected by the column address thereafter turns on a column transfer transistor for transferring data on the bit line to a data bus line, thereby transferring the data transferred to the bit line pair BL, /BL to data bus lines DB, /DB and outputting the data to outside of the device.
That is, in such operation, the bit line pair BL, /BL is precharged to a bit line precharge voltage VBLP in a standby mode before the DRAM device begins to operate and comes to have a minute potential difference therebetween as the data of the cell is transferred thereto when the device is operated. In this state, when the sense amplifier latch begins to operate, potentials of the bit line pair BL, /BL, which is maintained at a minute potential difference therebetween, go into the core potential Vcore and the ground potential Vss, respectively. The data on the bit lines having the amplified potentials is transferred to the data bus lines DB, /DB by a column decoder output signal yi.
However, at a time point where the sense amplifier latch applied with the core voltage VCORE as the sense amplifier bias voltage begins to operate, the core voltage is sharply lowered since a large current is consumed all at once. Therefore, to solve this problem, there is widely employed a method of shorting the external voltage VDD and the core voltage VCORE and applying the external voltage VDD with the core voltage VCORE at a time point where the sense amplifier begins to operate, and this is referred to as sense amplifier overdriving.
FIG. 1 is a block diagram illustrating a conventional sense amplifier circuit employed with sense amplifier overdriving.
As illustrated in FIG. 1, the conventional sense amplifier circuit includes a control signal generation unit 7, a sense amplifier driving unit 8 and a sense amplifier latch unit 9. The control signal generation unit 7 receives a sense amplifier enable signal SAEN for driving the sense amplifier circuit, and generates a first control signal SAP1B enabled for driving a first sense amplifier bias voltage RTO with the external voltage VDD, a second control signal SAP2B enabled for driving the first sense amplifier bias voltage RTO with the core voltage VCORE and a third control signal SAN enabled for driving a second sense amplifier bias voltage SB with the ground voltage VSS.
The sense amplifier driving unit 8 receives the first control signal SAP1B, the second control signal SAP2B and the third control signal SAN and drives the first sense amplifier bias voltage RTO and the second amplifier bias voltage SB. The sense amplifier latch unit 9 receives the first sense amplifier bias voltage RTO and the second amplifier bias voltage SB and latches the voltage of the bit line pair.
FIG. 2 shows waveforms of the first control signal SAP1B, the second control signal SAP2B and the third control signal SAN generated in the control signal generation unit 7. First, the first control signal SAP1B is enabled to a low level during a predetermined period after the sense amplifier enable signal SAEN is enabled to a high level (hereinafter, referred to as ‘overdriving period D’), and drives the first sense amplifier bias voltage RTO with the external voltage VDD. Next, the second control signal SAP2B is enabled to a low level during a period where the overdriving period D is terminated and the sense amplifier enable signal SAEN is enabled to a high level, and drives the first sense amplifier bias voltage RTO with the core voltage VCORE. Next, the third control signal SAN is enabled to a high level in a period where the sense amplifier enable signal SAEN is enabled to a high level, and drives the second sense amplifier bias voltage SB with a ground voltage VSS.
However, in the conventional sense amplifier circuit, the enable period of the first control signal SAP1B for setting the overdriving period is determined regardless of the level of the external voltage VDD. Therefore, there is a problem that when the level of the external voltage VDD is high, the overdriving period is too long and a leakage current flowing from the external voltage VDD to the core voltage VCORE is increased and thus current consumption is increased, and when the level of the external voltage VDD is low, a speed of driving the first sense amplifier voltage RTO is slowed down and the operation speed of the sense amplifier circuit is dropped.